The present invention relates generally to semiconductor memory devices, and more particularly to synchronous semiconductor memory devices having a frequency synchronous circuit that produces an internal signal for controlling the timing to read data.
A synchronous semiconductor memory reads and writes data synchronously with an external clock (CLK). As the frequency of a CLK signal in a synchronous semiconductor memory device, such as a synchronous dynamic random access memory (SDRAM), has increased, it has become necessary to decrease the data access time. A data access time can be the time from an external clock edge to the output of valid data. In an SDRAM the data access time may be determined by timing the data output with an internal signal ICLK (internal clock) produced by a delay operation. When it is difficult to realize the desired data access time with this approach, the data output timing can be controlled by an internal signal FICLK, which is generated by a synchronous circuit that has a frequency determined by the frequency of CLK. In a high speed memory device, such as a DDR (double data rate) SDRAM, data output is typically controlled by an FICLK signal produced by a synchronous circuit.
Various types of circuits may be used as the synchronous circuit. One such circuit is a DLL (delay locked loop). In this case, internal signal FICLK is produced by detecting a cycle of internal signal ICLK. In a semiconductor memory device that uses a synchronous circuit for outputting data, internal signal FICLK which is synchronized with the external CLK, will have a different timing than internal signal ICLK, which is synchronized with the external CLK.
In a read operation for a semiconductor memory device that uses a synchronous circuit, data output timing is controlled by using FICLK to trigger an output circuit to output data from the memory device. Depending on the construction of the data path, FICLK may also control the transmission of data in the data path upstream from the output circuit. For example, it may be used as the triggering signal for a data latch circuit, thus timing the transmission of data at a point before the data reaches the output circuit. This may be needed to improve operating margins when the data may not have propagated from the memory array to the data latch circuit at an earlier time in a read cycle. This will be explained below with reference to FIGS. 7, 8a and 8b. 
Referring to FIG. 7, a timing diagram illustrating data read timing in a semiconductor memory device is set forth. FIG. 7 shows the external clock CLK, internal signal ICLK, internal signal FICLK, and output data out.
As shown in FIG. 7, internal signal ICLK is generated at a delay of T1 after the rising edge of CLK. Internal signal FICLK is generated by the synchronous circuit based on the internal signal ICLK such that the rising edge of FICLK occurs at a time T2 from the rising edge of CLK. This is done by adjusting the synchronous circuit based on the knowledge of the time it takes data to propagate up to the output circuit. To prevent incorrect data from being output, the data must have propagated up to the output circuit by the time that the rising edge of FICLK is generated. FICLK can enable the output circuit and data can propagate to the output in a time of Tout.
Referring now to FIG. 8a, a block schematic diagram illustrating a portion of the data path in a semiconductor memory device is set forth and given the general reference character 800a. The data path 800a may include a data latch 801a and an output circuit 802a. The data latch 801a receives data on a data line and transmits the data to the output circuit 802a synchronously with the internal signal ICLK. The output circuit 802a receives the data from the data latch 801a and outputs the data synchronously with the internal signal FICLK. When the data path 800a is controlled as shown in FIG. 8a, the data patch 800a operation may be adversely affected as cycle times get smaller. For example, if a cycle time is 10 ns, T1=2 ns, and T2=2 ns, data can take 10 nsxe2x88x92T1xe2x88x92T2=6 ns to be transmitted through an output circuit, thus no problem will typically arise.
However, when the cycle time is 6 ns in the example above, data must be transmitted through an output circuit in 10 nsxe2x88x92T1xe2x88x92T2=2 ns, such a time may result in an operating margin that is insufficient due to propagation delays and bus capacitance. This may cause incorrect data to be transmitted in some cases. Thus, in the given example, when data is to be outputted in a time faster than or equal to 2 ns, the operating margin may be insufficient.
Referring now to FIG. 8b, a block schematic diagram illustrating a portion of the data path in a semiconductor memory device is set forth and given the general reference character 800b. The data path 800b may include a data latch 801b and an output circuit 802b. The data latch 801b receives data on a data line and transmits the data to the output circuit 802b synchronously with the internal signal FICLK. The output circuit 802a receives the data from the data latch 801b and also outputs the data synchronously with the internal signal FICLK.
In a data path 800b as illustrated in FIG. 8b, a timing for data transmission can be kept constant irrespective of the cycle time because internal signal FICLK is used both as triggering signal for the output circuit 800b and the data latch 800b. Accordingly, this configuration is effective when the synchronous circuit is used in a high speed memory device.
As in the above mentioned method, a synchronous circuit produces FICLK by detecting the cycle of the internal signal ICLK. A synchronous circuit""s ability to properly synchronize the internal clock FICLK with the internal clock ICLK is dependent on the frequency of the cycle and the design of the synchronous circuit. When the synchronous circuit is designed to permit synchronization with an excessively long (lower frequency) cycle, the area of the synchronous circuit is increased. Due to the increased sizes, inaccuracies may be magnified and thus operating characteristics can degenerate. Thus, a synchronous circuit is typically used under the premise that it will be operated at a relatively high frequency. The synchronous circuit is then designed to a scale that allows a certain operating margin with respect to a maximum (MAX) value of a CLK cycle time or a minimum CLK frequency.
In some cases, the MAX value of a CLK cycle time for the operation of the synchronous circuit cannot be achieved by a certain test setup. This is particularly true when the synchronous circuit is designed to operate at a high CLK frequency. In fact, sometimes the tester and/or test system is so limited that the test cannot be conducted at a high enough frequency for the synchronous circuit to properly operate. This is particularly true for tests such as multi-probe or laser-probe, which are performed on devices still in wafer form. In such cases, large parasitics caused by the test signal wirings, probes and/or probe contacts can slow operating frequencies. It is also particularly true on tests such as burn-in, in which large quantities of packaged parts are tested in parallel in order to drive out infant mortality and/or obtain statistical data on the devices in general.
In cases in which the test cannot be conducted at a high enough frequency to ensure the proper operation of the synchronous circuit, the semiconductor memory device is tested in a test mode in which the synchronous circuit is disabled. This particular case is shown in FIG. 9. Referring to FIG. 9, a timing diagram illustrating data read timing in a semiconductor memory device operating in a test mode, in which a synchronous circuit is disabled, is set forth. FIG. 9 shows the external clock CLK, internal signal ICLK, internal signal FICLK, and output data DATA. In the test mode operation of FIG. 9, the internal signal FICLK is not synchronized with the internal signal ICLK. Instead the internal signal FICLK is produced by a delay of the external CLK. Thus, the internal signal FICLK is generated with a timing equal to the timing of the internal signal ICLK or perhaps a timing later than the timing of ICLK due to a slight increase in the number of logic gates in which the internal signal FICLK must propagate through.
When operating under the test mode in which the synchronous circuit is disabled, timing of internal signal ICLK and the internal signal FICLK is different than the normal case in which the synchronous circuit is enabled. This creates a problem because circuits such as control (For example, Y address decoder which is controlled by internal signal ICLK) and data output circuits on the semiconductor memory device will be controlled at different timings in the test mode than in a normal mode. This problem can cause circuits to become more complex in order to improve operating margins for both the case where the synchronous circuit is enabled and the case where the synchronous circuit is disabled. Also, externally, the semiconductor memory device will be producing data at a different timing in the test mode than in a normal mode. Thus, it may become necessary to test the control system again and/or interface with another test on another tester. These problems can make the characterization of the semiconductor memory device more complex and unreliable.
In view of the above discussion, it would be desirable to provide a semiconductor memory device, such as an SDRAM, that operates in similar timings in both a normal mode in which a synchronous circuit is enabled and in a test mode in which a synchronous circuit is disabled.
According to the present invention, a semiconductor memory device having an internal signal generator that receives an external clock and generates internal signals. The internal signals having a time delay between them when the semiconductor memory operates in a normal mode of operation. In a test mode of operation the internal signal generator enables a signal delay path to enable the internal signals to have the same time delay between them in the test mode as the normal mode.
According to one aspect of the present invention, the internal signal generator includes a synchronous circuit that generates an internal signal by detecting the cycle time of an external clock.
According to another aspect of the present invention, the internal signal generator includes a timing control circuit that generates an internal signal. The timing control circuit includes a delay stage that delays the internal signal when the semiconductor memory device is in a test mode.
According to another aspect of the present invention. a first stage circuit receives an external clock and generates a first stage output. The timing control circuit receives the first stage output and generates an internal control signal that is delayed when in the test mode of operation as compared to a normal mode of operation.
According to another aspect of the invention, the timing control circuit includes a selection circuit that selects a signal path for the generation of an internal signal, which includes the delay circuit when in a test mode of operation and selects a signal path without the delay circuit when in a normal mode of operation. The selection circuit includes transfer gates controllable by a test mode signal.
According to another aspect of the invention, the synchronous circuit receives a first stage output and generates an internal signal. The synchronous circuit correctly operates at a certain frequency range in the normal mode of operation. The test mode is operated at a frequency range in which the frequency circuit does not operate correctly. The internal signal from the synchronous circuit has the same timing as internal signal from the timing control circuit when in the test mode of operation as in the normal mode of operation.
According to another aspect of the present invention, a timing control circuit receives the output of a synchronous circuit and generates an internal signal being delayed by the timing control circuit when operating in a test mode as compared to the delay when operating in a normal mode. The delay being adjustable for operation at various clock frequencies.
According to another aspect of the present invention, an output circuit is synchronously controlled by an internal signal generated by an internal signal generator, such that the internal signals have the same timing with respect to each other in a normal mode of operation as in a test mode of operation.
According to another aspect of the present invention, a first and second internal signal generators that receive a first and second external clock and generate internal signals. The internal signals having a time delay between them when the semiconductor memory operates in a normal mode of operation. In a test mode of operation the first and second internal signal generators enable signal delay paths to enable the internal signals to have the same time delay between them in the test mode as the normal mode.